| I Semester |
|
| Report and Orientation programme | 05.12.2011to 09.12.2011 (5days) |
| I Spell of Instructions | 12.12.2011 to 04.02.2012 (8w) |
| I Mid of Examination | 06.02.2012 to 11.02.2012 (1w) |
| II Spell of Instructions | 13.02.2012 to 07.04.2012 (8w) |
| II Mid of Examination | 09.04.2012 to 14.04.2012 (1w) |
| Preparation and practical Examinations | 16.04.2012 to 28.04.2012 (2w) |
| End semester examinations | 30.04.2012 to 12.05.2012 (2w) |
| Summer vacation | 13.05.2012 TO 03.06.2012 |
| Commencement of class work for II Sem | 04.06.2012 |
| II Semester |
|
| I Spell of Instructions | 04.06.2012 to 28.07.2012 (8w) |
| I Mid of Examination | 30.07.2012 to 04.08.2012 (1w) |
| II Spell of Instructions | 06.08.2012 to 29.09.2012 (8w) |
| II Mid of Examination | 01.10.2012 to 06.10.2012 (1w) |
| Preparation and practical Examinations | 08.10.2012 to 20.10.2012 (2w) |
| End semester examinations | 22.10.2012 to 03.11.2012 (2w) |
Wednesday, January 11, 2012
JNTUH, Academic Calendar for M. Tech course – I, II semesters for the regular batch commencing in the academic year 2011-12
Sunday, January 8, 2012
JNTUH MTECH VLSI SYSTEM DESIGN R09 SYLLABUS
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY
M.Tech. VLSI SYSTEM DESIGN
COURSE STRUCTURE AND SYLLABUS
I YEAR - I Semester
| Code | Group | Subject | L | P | Credits |
| | | Microcontrollers for Embedded System Design | 3 | 0 | 3 |
| | | CPLD & FPGA Architectures and Applications | 3 | 0 | 3 |
| | | VLSI Technology & Design | 3 | 0 | 3 |
| | | Algorithms for VLSI Design Automation | 3 | 0 | 3 |
| | Elective -I | Hardware Software Co-Design | 3 | 0 | 3 |
| | | Digital System Design | | | |
| | | Device Modeling | | | |
| | Elective -II | Advanced Digital Signal Processing | 3 | 0 | 3 |
| | | Network Security & Cryptography | | | |
| | | Micro Electromechanical Systems | | | |
| | Lab | Simulation Lab (VLSI) | 0 | 3 | 2 |
| | | Seminar | - | - | 2 |
| | | Total Credits (6 Theory + 1 Lab.) | | | 22 |
I Year – I Sem. M.Tech (VLSI System Design)
MICROCONTROLLERS FOR EMBEDDED SYSTEM DESIGN
Unit – I: Introduction to Embedded Systems
Overview of Embedded Systems, Processor Embedded into a system, Embedded Hardware Units and Devices in system, Embedded Software, Complex System Design, Design Process in Embedded System, Formalization of System Design, Classification of Embedded Systems.
Unit – II: Microcontrollers and Processor Architecture & Interfacing
8051 Architecture, Input/Output Ports and Circuits, External Memory, Counters and Timers, PIC Controllers. Interfacing Processor (8051, PIC), Memory Interfacing, I/O Devices, Memory Controller and Memory arbitration Schemes.
Unit – III: Embedded RISC Processors & Embedded System-on Chip Processor
PSOC (Programmable System-on-Chip) architectures, Continuous Timer blocks, Switched Capacitor blocks, I/O blocks, Digital blocks, Programming of PSOC, Embedded RISC Processor architecture – ARM Processor architecture, Register Set, Modes of operation and overview of Instructions
Unit – IV: Interrupts & Device Drivers
Exceptions and Interrupt handling Schemes – Context & Periods for Context Switching, Deadline & interrupt latency. Device driver using Interrupt Service Routine, Serial port Device Driver, Device drivers for Internal Programmable timing devices
Unit – V: Network Protocols
Serial communication protocols, Ethernet Protocol, SDMA, Channel & IDMA, External Bus Interface
TEXT BOOKS:
1. Embedded Systems - Architecture Programming and Design – Raj Kamal, 2nd ed., 2008,TMH.
2. PIC Microcontroller and Embedded Systems – Muhammad Ali Mazidi, Rolin D.Mckinaly, Danny Causy – PE.
3. Designers Guide to the
REFERENCES:
1. Embedded Microcomputer Systems, Real Time Interfacing – Jonathan W. Valvano – Brookes / Cole, 1999, Thomas Learning.
2. ARM Systems Developers Guides- Design & Optimizing System Software - Andrew N. Sloss, Dominic Symes, Chris Wright, 2004, Elsevier.
3. Designing with PIC Microcontrollers- John B. Peatman, 1998, PH Inc.
I Year – I Sem. M.Tech (VLSI System Design)
CPLD AND FPGA ARCHITECTURE AND APPLICATIONS
UNIT –I
Programmable logic : ROM, PLA, PAL PLD, PGA – Features, programming and applications using complex programmable logic devices Altera series – Max 5000/7000 series and Altera FLEX logic-10000 series CPLD, AMD’s- CPLD (Mach 1to 5), Cypres FLASH 370 Device technology, Lattice PLST’s architectures – 3000 series – Speed performance and in system programmability.
UNIT – II
FPGAs: Field Programmable gate arrays- Logic blocks, routing architecture, design flow technology mapping jfor FPGAs, Case studies Xitir x XC4000 & ALTERA’s FLEX 8000/10000 FPGAs: AT &T ORCA’s ( Optimized Reconfigurable Cell Array): ACTEL’s ACT-1,2,3 and their speed performance
UNIT-III
Alternative realization for state machine chat suing microprogramming linked state machine one –hot state machine, petrinetes for state machines-basic concepts, properties, extended petrinetes for parallel controllers.
UNIT-IV
Digital front end digital design tools for FPGAs& ASICs: Using mentor graphics EDA tool (“FPGA Advantage”) – Design flow using FPGAs
UNIT - V
Case studies of paraller adder cell paraller adder sequential circuits, counters, multiplexers, parellel controllers.
TEXT BOOKS:
1. Field Programmable Gate Array Technology -
2. Field Programmable Gate Arrays, John V.Oldfield, Richard C Dore, Wiley Publications.
REFERENCES :
1. Digital Design Using Field Programmable Gate Array, P.K.Chan & S. Mourad, 1994, Prentice Hall.
2. Digital System Design using Programmable Logic Devices – Parag.K.Lala, 2003, BSP.
3. Field programmable gate array, S. Brown, R.J.Francis, J.Rose ,Z.G.Vranesic, 2007, BSP.
4. Digital Systems Design with FPGA’s and CPLDs – Ian Grout, 2009, Elsevier.
I Year – I Sem. M.Tech (VLSI System Design)
VLSI TECHNOLOGY & DESIGN
UNIT – I:
Review of Microelectronics and Introduction to MOS Technologies: MOS, CMOS, BiCMOS Technology, Trends And Projections.
Basic Electrical Properties of MOS, CMOS & BiCMOS Circuits: Ids-Vds relationships, Threshold Voltage Vt, Gm, Gds and ωo, Pass Transistor, MOS, CMOS & Bi CMOS Inverters, Zpu/Zpd, MOS Transistor circuit model, Latch-up in CMOS circuits.
UNIT – II:
LAYOUT DESIGN AND TOOLS: Transistor structures, Wires and Vias, Scalable Design rules, Layout Design tools.
LOGIC GATES & LAYOUTS: Static Complementary Gates, Switch Logic, Alternative Gate circuits, Low power gates, Resistive and Inductive interconnect delays.
UNIT – III:
COMBINATIONAL LOGIC NETWORKS: Layouts, Simulation, Network delay, Interconnect design, Power optimization, Switch logic networks, Gate and Network testing.
UNIT –IV:
SEQUENTIAL SYSTEMS: Memory cells and Arrays, Clocking disciplines, Design, Power optimization, Design validation and testing.
UNIT – V:
FLOOR PLANNING & ARCHITECTURE DESIGN: Floor planning methods, off-chip connections, High-level synthesis, Architecture for low power, SOCs and Embedded CPUs, Architecture testing.
TEXT BOOKS:
1. Essentials of VLSI Circuits and Systems, K. Eshraghian Eshraghian. D, A.Pucknell, 2005, PHI.
2. Modern VLSI Design - Wayne Wolf, 3rd ed., 1997, Pearson Education.
REFERENCES:
1. Principals of CMOS VLSI Design – N.H.E Weste, K.Eshraghian, 2nd ed., Adisson Wesley.
I Year – I Sem. M.Tech (VLSI System Design)
ALGORITHMS FOR VLSI DESIGN AUTOMATION
UNIT I
PRELIMINARIES
Introduction to Design Methodologies, Design Automation tools, Algorithimic Graph Theory, Computational complexity, Tractable and Intractable problems.
UNIT II
GENERAL PURPOSE METHODS FOR COMBINATIONAL OPTIMIZATION
Backtracking, Branch and Bound, Dynamic Programming, Integer Linear Programming,
Local Search, Simulated Annealing, Tabu search, Genetic Algorithms.
UNIT III
LAYOUT COMPACTION, PLACEMENT, FLOORPLANNING AND ROUTING
Problems, Concepts and Algorithms.
UNIT IV
MODELLING AND SIMULATION
Gate Level Modelling and Simulation, Switch level Modelling and Simulation.
UNIT V
LOGIC SYNTHESIS AND VERIFICATION
Basic issues and Terminology, Binary-Decision diagrams, Two-Level logic Synthesis
UNIT VI
HIGH-LEVEL SYNTHESIS
Hardware Models, Internal representation of the input Algorithm, Allocation, Assignment and Scheduling, Some Scheduling Algorithms, Some aqspects of Assignment problem, High-level Transformations.
UNIT VII
PHYSICAL DESIGN AUTOMATION OF FPGA’S
FPGA technologies, Physical Design cycle for FPGA’s, partitioning and Routing for segmented and staggered Models.
UNIT VIII
PHYSICAL DESIGN AUTOMATION OF MCM’S
MCM technologies, MCM phsical design cycle, Partitioning, Placement - Chip Array based and Full Custom Approaches, Routing – Maze routing, Multiple stage routing, Topologic routing, Integrated Pin – Distribution and routing, Routing and Programmable MCM’s.
TEXT BOOKS:
1. Algorithms for VLSI Design Automation, S.H.Gerez, 1999, WILEY Student Edition, John wiley & Sons (
2. Algorithms for VLSI Physical Design Automation – Naveed Sherwani, 3rd Ed., 2005, Springer International Edition.
REFERENCES:
1. Comoputer Aided Logical Design with Emphasis on VLSI – Hill & Peterson, 1993, Wiley.
2. Modern VLSI Design:Systems on silicon – Wayne Wolf, 2nd ed., 1998, Pearson Education Asia.
I Year – I Sem. M.Tech (VLSI System Design)
HARDWARE- SOFTWARE CO- DESIGN
(ELECTIVE-I)
UNIT –I
CO- DESIGN ISSUES
Co- Design Models, Architectures, Languages, A Generic Co-design Methodology.
CO- SYNTHESIS ALGORITHMS :
Hardware software synthesis algorithms: hardware – software partitioning distributed system co-synthesis.
UNIT –II
PROTOTYPING AND EMULATION:
Prototyping and emulation techniques, prototyping and emulation environments, future developments in emulation and prototyping architecture specialization techniques, system communication infrastructure
TARGET ARCHITECTURES:
Architecture Specialization techniques, System Communication infrastructure, Target Architecture and Application System classes, Architecture for control dominated systems (8051-Architectures for High performance control), Architecture for Data dominated systems (ADSP21060, TMS320C60), Mixed Systems.
UNIT – III
COMPILATION TECHNIQUES AND TOOLS FOR EMBEDDED PROCESSOR
ARCHITECTURES:
Modern embedded architectures, embedded software development needs, compilation technologies practical consideration in a compiler development environment.
UNIT – IV
DESIGN SPECIFICATION AND VERIFICATION:
Design, co-design, the co-design computational model, concurrency coordinating concurrent computations, interfacing components, design verification, implementation verification, verification tools, interface verification
UNIT – V
LANGUAGES FOR SYSTEM – LEVEL SPECIFICATION AND DESIGN-I
System – level specification, design representation for system level synthesis, system level specification languages,
LANGUAGES FOR SYSTEM – LEVEL SPECIFICATION AND DESIGN-II
Heterogeneous specifications and multi language co-simulation the cosyma system and lycos system.
TEXT BOOKS :
1. Hardware / software co- design Principles and Practice – Jorgen Staunstrup, Wayne Wolf – 2009, Springer.
2. Hardware / software co- design Principles and Practice, 2002, kluwer academic publishers
I Year – I Sem. M.Tech (VLSI System Design)
DIGITAL SYSTEM DESIGN
(ELECTIVE-I)
Unit-I: Designing with Programmable Logic Devices
Designing with Read only memories – Programmable Logic Arrays – Programmable Array logic – Sequential Programmable Logic Devices – Design with FPGA’s– Using a One-hot state assignment,
State transition table- State assignment for FPGA’s - Problem of Initial state assignment for One –Hot encoding - State Machine charts – Derivation of SM Charts – Realization of SM charts – Design Examples –Serial adder with Accumulator - Binary Multiplier – Signed Binary number multiplier (2’s Complement multiplier) – Binary Divider – Control logic for Sequence detector – Realization with Multiplexer – PLA – PAL.
Unit-II: Fault Modeling & Test Pattern Generation
Logic Fault model – Fault detection & Redundancy- Fault equivalence and fault location –Fault dominance – Single stuck at fault model – Multiple stuck at fault models –Bridging fault model
Fault diagnosis of combinational circuits by conventional methods – Path sensitization techniques, Boolean Difference method – Kohavi algorithm – Test algorithms – D algorithm, PODEM, Random testing, Transition count testing, Signature analysis and test bridging faults.
Unit-III: Fault Diagnosis in Sequential Circuits
Circuit Test Approach, Transition Check Approach - State identification and fault detection experiment, Machine identification, Design of fault detection experiment.
Unit-IV: PLA Minimization and Testing
PLA Minimization – PLA folding, Fault model in PLA, Test generation and Testable PLA Design.
Unit-V: Minimization and Transformation of Sequential Machines
The Finite state Model – Capabilities and limitations of FSM – State equivalence and machine minimization – Simplification of incompletely specified machines.
Fundamental mode model – Flow table – State reduction – Minimal closed covers – Races, Cycles and Hazards.
TEXT BOOKS:
1. Fundamentals of Logic Design – Charles H. Roth, 5th ed., Cengage Learning.
2. Digital Systems Testing and Testable Design – Miron Abramovici, Melvin A. Breuer and Arthur D. Friedman- John Wiley & Sons Inc.
3. Logic Design Theory – N. N. Biswas, PHI
REFERENCES:
1. Switching and Finite Automata Theory – Z. Kohavi , 2nd ed., 2001, TMH
2. Digital Design – Morris Mano, M.D.Ciletti, 4th Edition, PHI.
3. Digital Circuits and Logic Design – Samuel C. Lee , PHI
I Year – I Sem. M.Tech (VLSI System Design)
DEVICE MODELLING
(ELECTIVE-I)
UNIT I:
Introduction to Semiconductor Physics: Review of Quantum Mechanics, Boltzman transport equation, continuity equation, Poisson equation
Integrated Passive Devices: Types and Structures of resistors and capacitors in monolithic technology, dependence of model parameters on structures
UNIT II:
Integrated Diodes: Junction and Schottky diodes in monolithic technologies – static and dynamic behavior – small and large signal models – SPICE models
Integrated Bipolar Transistor: Types and structures in monolithic technologies – Basic model (Eber-Moll) – Gunmel - Poon model- dynamic model, parasitic effects – SPICE model –parameter extraction
UNIT III:
Integrated MOS Transistor: nMOS and pMOS transistor – threshold voltage – threshold voltage equations – MOS device equations – Basic DC equations second order effects – MOS models – small signal AC characteristics – MOS FET SPICE model level 1, 2, 3 and 4
UNIT IV:
VLSI Fabrication Techniques: An overview of wafer fabrication, wafer processing – oxidation – patterning – diffusion – ion implantation – deposition – Silicon gate nMOS process – CMOS processes – n-well- p-well- twin tub- Silicon on insulator – CMOS process enhancements – interconnects circuit elements
UNIT V:
Modeling of Hetero Junction Devices: Band gap Engineering, Bandgap Offset at abrupt Hetero Junction, Modified current continuity equations, Hetero Junction bipolar transistors (HBTs), SiGe
TEXT BOOKS:
1. Introduction to Semiconductor Materials and Devices – Tyagi M. S, 2008, John Wiley Student Edition.
2. Solid state circuits – Ben G. Streetman, Prentice Hall, 1997
REFERENCES:
1. Physics of Semiconductor Devices – Sze S. M, 2nd edition, Mcgraw hill,
1. Introduction to Device Modeling and Circuit Simulation – Tor A. Fijedly, Wiley-Interscience, 1997.
I Year – I Sem. M.Tech (VLSI System Design)
ADVANCED DIGITAL SIGNAL PROCESSING E
(ELECTIVE-II)
UNIT I
Review of DFT, FFT, IIR Filters, FIR Filters,
Multirate Signal Processing: Introduction, Decimation by a factor D, Interpolation by a factor I, Sampling rate conversion by a rational factor I/D, Multistage Implementation of Sampling Rate Conversion, Filter design & Implementation for sampling rate conversion, Applications of Multirate Signal Processing
UNIT II
Non-Parametric methods of Power Spectral Estimation: Estimation of spectra from finite duration observation of signals, Non-parametric Methods:
UNIT III
Parametric Methods of Power Spectrum Estimation: Autocorrelation & Its Properties, Relation between auto correlation & model parameters, AR Models - Yule-Waker & Burg Methods, MA & ARMA models for power spectrum estimation.
UNIT –IV
Linear Prediction : Forward and Backward Linear Prediction – Forward Linear Prediction, Backward Linear Prediction, Optimum reflection coefficients for the Lattice Forward and Backward Predictors. Solution of the
UNIT V
Finite Word Length Effects: Analysis of finite word length effects in Fixed-point DSP systems – Fixed, Floating Point Arithmetic – ADC quantization noise & signal quality – Finite word length effect in IIR digital Filters – Finite word-length effects in FFT algorithms.
TEXTBOOKS:
1. Digital Signal Processing: Principles, Algorithms & Applications - J.G.Proakis & D.G.Manolokis, 4th ed.,
PHI.
2. Discrete Time signal processing - Alan V Oppenheim & Ronald
3. DSP – A Pratical Approach – Emmanuel C.Ifeacher, Barrie. W. Jervis, 2 ed., Pearson Education.
REFERENCES:
1. Modern spectral Estimation : Theory & Application – S. M .Kay, 1988, PHI.
2. Multirate Systems and Filter Banks – P.P.Vaidyanathan – Pearson Education
3. Digital Signal Processing – S.Salivahanan, A.Vallavaraj, C.Gnanapriya, 2000,TMH
I Year – I Sem. M.Tech (VLSI System Design)
NETWORK SECURITY AND CRYPTOGRAPHY
(ELECTIVE-II)
UNIT-I
Introduction:
Attacks, Services and Mechanisms, Security attacks, Security services, A Model for Internetwork security.Classical Techniques: Conventional Encryption model, Steganography, Classical Encryption Techniques.
UNIT-II
Modern Techniques:
Simplified DES, Block Cipher Principles, Data Encryption standard, Strength of DES, Differential and Linear Cryptanalysis, Block Cipher Design Principles and Modes of operations.
Algorithms: Triple DES, International Data Encryption algorithm, Blowfish, RC5, CAST-128, RC2, Characteristics of Advanced Symmetric block cifers.
UNIT-III
Conventional Encryption
Placement of Encryption function, Traffic confidentiality, Key distribution, Random Number Generation.
Public Key Cryptography
Principles, RSA Algorithm, Key Management, Diffie-Hellman Key exchange, Elliptic Curve Cryptography.
UNIT-IV
Number theory
Prime and Relatively prime numbers, Modular arithmetic, Fermat’s and Euler’s theorems, Testing for primality,
Message authentication and Hash functions:
Authentication requirements and functions, Message Authentication, Hash functions, Security of Hash functions and MACs.
UNIT-V
Hash and Mac Algorithms
MD File, Message digest Algorithm, Secure Hash Algorithm, RIPEMD-160, HMAC. Digital signatures and Authentication protocols:
Digital signatures, Authentication Protocols, Digital signature standards.
UNIT-VI
Authentication Applications:
Kerberos, X.509 directory Authentication service.Electronic Mail Security: Pretty Good Privacy, S/MIME.
UNIT-VII
IP Security
Overview, Architecture, Authentication, Encapsulating Security Payload, Combining security Associations, Key Management.
Web Security
Web Security requirements, Secure sockets layer and Transport layer security, Secure Electronic Transaction.
UNIT-VIII
Intruders, Viruses and
Fire Walls : Fire wall Design Principles, Trusted systems.
TEXT BOOKS:
1. Cryptography and Network Security: Principles and Practice - William Stallings, 2000, PE.
REFERENCES:
1. Principles of Network and Systems Administration, Mark Burgess,John Wiel
I Year – I Sem. M.Tech (VLSI System Design)
MICRO ELECTROMECHANICAL SYSTEMS
(ELECTIVE-II)
UNIT –I
Introduction, basic structures of MEM devices – (Canti-Levers, Fixed Beams diaphragms). Broad Response of Micro electromechanical systems (MEMS) to Mechanical (Force, pressure etc.) Thermal, Electrical, optical and magnetic stimuli, compatibility of MEMS from the point of power dissipation, leakage etc.
UNIT –II
Review of mechanical concepts like stress, strain, bending moment, deflection curve. Differential equations describing the deflection under concentrated force, distributed force, distributed force, deflection curves for canti-levers- fixed beam. Electrostatic excitation – columbic force between the fixed and moving electrodes. Deflection with voltage in C.L, Deflection Vs Voltage curve, critical fringe field – field calculations using
UNIT – III
Two terminal MEMS - capacitance Vs voltage Curve – variable capacitor. Applications of variable capacitors. Two terminal MEM structures.
Three terminal MEM structures – controlled variable capacitors – MEM as a switch and possible applications.
UNIT – IV
MEM circuits & structures for simple GATES- AND, OR, NAND, NOR, Exclusive OR
UNIT – V
MEM Technologies: Silicon based MEMS- process flow – brief account of various processes and layers like fixed layer, moving layers spacers etc., and etching technologies.
Metal Based MEMS: Thin and thick film technologies for MEMS. Process flow and description of the processes. Status of MEMS in the current electronics scenario.
TEXT BOOKS:
1. MEMS Theory, Design and Technology - GABRIEL. M.Review, R.F.,2003, John wiley & Sons. .
2. Strength of Materials –Thimo Shenko, 2000, CBS publishers & Distributors.
3. MEMS and NEMS, Systems Devices; and Structures - Servey E.Lyshevski, 2002, CRC Press.
REFERENCES:
1. Sensor Technology and Devices - Ristic L. (Ed) , 1994, Artech House,
I Year – I Sem. M.Tech (VLSI System Design)
SIMULATION LAB (VLSI)
CYCLE 1:
1. Digital Circuits Description using Verilog.
2. Verification of the functionality of designed Circuits using function simulator.
3. Timing Simulation for critical Path time calculation.
4. Synthesis of Digital Circuits.
5. Place and route techniques for major FPGA Vendors using Xilinx, Altera, Cypress etc.,
6. Implementation of Designed Digital Circuits Using FPGA and CPLD devices.
CYCLE 2:
1. MoS inverter DC Characteristics, AC Characteristics, Transient Analysis.
2. NMOS, PMOS Characteristics.
3. Layout basics- INV, NAND, NOR, EXOR, EXNOR.
4. Layout of adder, subtractor, multiplexer.
5. Layout Comparator.
For Experiments in cycle 2: 3,4,5: Draw the Schematics Perform Simulation, Extract the Layout, Run Physical Verification (DRC, LVS, PEX) and post layout simulation.